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Reconfigurable and Adaptive Computing : Theory and Applications

By: (Edited by) Chao Wang , (Edited by) Chao Wang , (Edited by) Nadia Nedjah , (Edited by) Nadia Nedjah

Extended Catalogue

Ksh 36,000.00

Format: Hardback or Cased Book

ISBN-10: 1498731759

ISBN-13: 9781498731751

Publisher: Taylor & Francis Inc

Imprint: Chapman & Hall/CRC

Country of Manufacture: US

Country of Publication: GB

Publication Date: Dec 1st, 2015

Print length: 246 Pages

Weight: 542 grams

Dimensions (height x width x thickness): 16.40 x 24.10 x 1.80 cms

Product Classification: Systems analysis & design

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This book explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems. It describes new, practical solutions to issues with computer and network security systems, next-generation sequencing, and more, and discusses improved approaches to video watermarking, routing, and system performance.

Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems.

The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators.

The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies.

The final section addresses the methodology of system codesign. The book introduces a new software–hardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task software–hardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.


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